Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops

Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops

Speaker Name: 
Luciano Lavagno
Speaker Title: 
Full Professor
Speaker Organization: 
Department of Electronics and Telecommunications of the Politecnico di Torino
Start Time: 
Thursday, January 18, 2024 - 2:00pm
End Time: 
Thursday, January 18, 2024 - 3:00pm
E506 or https://ucsc.zoom.us/j/95458850497?pwd=VWhGaFdkK1pJRmZwQUtlWDFLTWpUdz09



Flip-flops (FFs) are the most commonly used sequential elements in synchronous circuits, but their timing requirements limit the operating frequency. Borrowing time with a latch-based approach can increase operating frequency, but traditional back-end optimization tools struggle to manage hold time requirements. The Mix & Latch technique achieves higher frequencies and often lower area than commercial state-of-the-art retiming by exploiting four types of synchronous sequential gates, namely positive and negative edge-triggered FFs and positive and negative transparent latches, all using a single clock tree. The effectiveness of Mix & Latch is demonstrated on both standard logic synthesis benchmarks and on a RISC-V processor core from the Pulp platform using 28 nm CMOS FDSOI technology. The results are compared to retiming performed with a state-of-the-art tool, showing a 25 % frequency improvement over the traditional design flow and 7.5 % over the retiming flow. Compared to the retiming flow, we achieve comparable or lower power and area, while preserving the original registers and allowing logic equivalence checking.


Speaker Bio

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley (California, USA) in 1992 and from Politecnico di Torino (Italy) in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, the CRC Handbook on Electronic Design Automation, and over 250 scientific papers. He has been granted 13 US patents. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he has been one of the creators and architects of the Cadence C-to-Silicon high-level synthesis system. Between 2015 and 2017 he has worked, with the Calypto group of Mentor Graphics, on their high level synthesis tool, called Catapult. Since 2018 he has been leading the back-end team working on the Vitis HLS tool from Xilinx/AMD. Since 2011 he is also a full professor with Politecnico di Torino, Italy. Luciano has been serving for many years on the technical committees of the main international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) and of various workshops and symposia. He has been the technical program chair of DAC, and the TPC and general chair of CODES.  A senior member of IEEE, Luciano has been also associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits, in particular for acceleration of Machine Learning tasks, performance optimization of digital circuits, including asynchronous and Razor-like design techniques, as well as circuits and algorithms for indoor localization and tracking.