A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS
Submitted by kachaffi on September 6, 2017 - 11:31am
Title | A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS |
Publication Type | Conference Paper |
Year of Publication | 2016 |
Authors | Ataei S, Stine JE, Guthaus MR |
Conference Name | Computer Design (ICCD), 2016 IEEE 34th International Conference on |
Publisher | IEEE |